Increased design complexity in AMS designs along with an increase in the number of design engineers spread across multi sites makes it difficult for designers to deliver successful tapeouts within the ever shortening design schedules.To help design engineers meet the challenges, Cadence & ClioSoft have worked together to provide solutions to tackle the design complexity as well as collaborate efficiently on successful tapeouts.
Join us for a talk by Steve Lewis, Director of Marketing from Cadence Designs Systems to learn about the new analog design suite - Virtuoso® ADE Explorer, Virtuoso® ADE Assembler, Virtuoso® Variation Option and the Virtuoso® ADE Verifier - and the new Maestro view. Learn from the webinar to see how Virtuoso IC6.1.7 can meet your design requirements and allows users to flexibly select the product that best supports their design goals as they move through the design flow. This will be accompanied by a presentation from Karim Khalfan, Director Application Engineering at ClioSoft showcasing the tight integration of the SOS7 design management platform with the Cadence Virtuoso platform, including support for maestro views and the improved performance using IC6.1.7.
The SOS platform from ClioSoft is the leading design data and IP management platform for hardware design engineers. The only data management platform built for digital, analog, RF and mixed-signal designs, SOS empowers design teams located in single or multiple design centers to collaborate efficiently on their designs.
IP Management from ClioSoft helps semiconductor companies catalog and manage various internal and third-party IPs thereby improving design reuse within a company. With an easy-to-use administration and user cockpit, ClioSoft provides enterprise-level IP Management to manage the process of creating IPs and their derivatives, their lineage, IP licensing, security, issue and defect tracking.
This great event is on June 1st to 15th, 2014.