The increase in complexity of designs and process kits along with tight design schedules has lead to an increase in the number of designers in most semiconductor companies. Ad hoc methodologies that worked in the past among SoC design groups do not necessarily work correctly today due to design and process complexity as well as the large number of designers whose work has to coordinated. Design team managers and engineers now need quick answers to questions such as
- What design changes have been checked in this week?
- Is the layout for this design DRC/LVS clean?
- The design was working yesterday. What changed?
- Which revision of the schematic was the layout created for?
- Which designs have been completed and frozen?
- Looks like the schematic had some ECOs! What exactly changed?
Without the presence of a design data management system and a formal process on how to collaborate among geographically dispersed designers and design groups, a lot of productivity is wasted and engineers may create spurious errors that takes considerable time to rectify.
View the webinar recording where we demonstrate a non-intrusive flow for design team collaboration using ClioSoft's SOS Design Collaboration Platform integrated with Cadence Virtuoso® technology. Click here to see how both local and remote design teams can quickly and effectively collaborate on IP integration for SoC creation by using the SOS data management platform.